SpaceCube v2.0 Processor with DDR2 Memory Upgrade

This new version of the card assembly will feature a total of eight 4x DDR2 SDRAM memories per Xilinx FPGA. A dedicated regulator was included to compensate for the lower operating voltage of DDR2 in comparison to the older DDR memory. The DDR2 memories are grouped in pairs with shared address/command/control lines. By sharing those lines, the number of Xilinx I/Os for the DDR2 interfaces could be reduced. These improvements extend the life and design of the processor and provide even greater memory throughput to support the next generation of instruments. The DDR SDRAM memory dies that had been radiation tested and flight qualified have reached end of life. The remaining stock of DDR SDRAM is rapidly dwindling and future projects will require a change to DDR2 SDRAM. Additionally, the next generation of instruments are set to produce even greater amounts of science data and require even more memory bandwidth for on-board processing. Switching to DDR2 improves support for new instruments because it can provide more than a 2x memory speedup over the DDR1 design.