Space-Time Compressed Sampling Techniques for Integrated Ultrasound Imaging System-on-a-Chip

PROJECT SUMMARY The rapidly growing needs of portable and wearable ultrasound imaging systems call for compact, energy- efficient integration of ultrasound front-end electronics. On-chip data reduction and digitization are crucial aspects to bridge the gap between the high-performance imaging requirements and the stringent constraints in power, physical size and interconnects. The classic methods of analog micro-beamforming and time-domain multiplexing suffer from undesirable trade-offs of losing raw RF data or low frame rate, prohibiting their usage for many important emerging imaging modalities such as high frame rate plane wave imaging and correlation- based modalities such as shear wave elastography. This proposal seeks to explore a new approach for efficient ultrasound electronics integration that allows access to pre-beamformed RF data with manageable digital data rates and uncompromised imaging speed, through studying the application of compressed sensing (CS) to ultrasound imaging at the integrated circuit level. The PI and Co-I propose to develop a novel CS framework that performs spatial and temporal compression of full channel RF data compression together with the analog-to- digital conversion, enabling concurrent reduction on the data volume, sampling rate, and circuit footprint. A prototype CS digital ultrasound SoC containing on-chip ADCs and data links and fully compatible with potentially catheter-based reduced cable imaging will be designed, implemented, and benchmarked against conventional imaging systems. The long-term goal of this exploratory research program is to lay the foundations for next generation integrated front-end circuits for medical ultrasound imaging, providing the important theories, models, circuit techniques, as well as the design space and limitations for emerging portable and wearable systems.