CAREER: Designing Next-Generation Programmable Switches for Stateful In-Network Computing

Stateful In-network computing (where users can run custom programs with custom state in the network data plane) has been shown to improve the performance of a wide-range of key applications from domains ranging from networking to distributed systems to databases to machine learning. Unfortunately, the enabling technology for stateful In-network computing, namely the programmable switches, have fundamental design limitations that prevent them from scaling to the growing demands of both the current and emerging In-network applications. In particular, current generation of programmable switches cannot simultaneously run large number of applications, cannot store large amounts of state needed for state-intensive applications, and cannot scale to line rate processing for certain stateful applications. This project will investigate the design of next-generation programmable switches that could simultaneously run large number of applications, store and process large amounts of state, while running at multi-Tbps line rate, at the cost of only a nominal increase in chip area and power consumption compared to current programmable switches. The limitations of current programmable switches were studied previously in the context of microprocessor-based network processors from the early 2000s. However, the fundamental difference in the processing architecture and line rate of microprocessor-based network processors compared to current programmable switches, has opened an opportunity to re-visit these problems in a completely new light. In that regard, this project will make three key innovations. First, the project will investigate new ways to store and access shared state across multiple parallel switch pipelines for achieving line rate processing for stateful applications. Second, the project will investigate ways to dynamically allocate and share switch resources at line rate, providing an abstraction of a "virtual" programmable switch to each application, in order to scale to large number of applications. And finally, the project will investigate optimal cache designs (between on-chip SRAM and off-chip DRAM) that allow visibility into future requests at runtime through co-ordination between neighbor switches in the network, to support state-intensive applications at line rate. This project also proposes several educational and outreach initiatives that will be tightly integrated with the proposed research. The systems and applications developed as part of this project will be integrated into the curriculum of both the existing and new courses at Purdue, including courses from non-networking domains, such as distributed systems and computer architecture. As part of the K-12 and underrepresented minority outreach, this project will organize an annual 1-week summer workshop at Purdue targeting high-school and incoming undergraduate students belonging to communities historically underrepresented in computer science and engineering, to encourage them to pursue a career in science and engineering by giving them hands-on experience with state-of-the-art networking technologies developed as part of this project. All the results and artifacts from this project, including the source code, will be made publicly and permanently available at the URL https://github.com/vishal1303. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.