Collaborative Research: SHF: Medium: A hardware-software co-design approach for high-performance in-memory analytic data processing

Database analytics is crucial for decision-making across various industries and fields of inquiry. However, there is a challenge: analyzing large amounts of data using traditional methods takes more time and money as the volume of data grows. Resolving this issue is vital for enterprises to stay competitive through fast and accurate data-driven decision-making and to keep up with rapid growth in data volumes. In the past, hardware and software for analytics could be developed separately, benefiting from Moore's Law (doubling of transistor density with each transistor generation) and Dennard scaling (which allowed Moore's Law to proceed without increasing power density). This scaling allowed the industry to steadily improve the performance of general-purpose hardware. However, we have now reached the physical limits of these trends and need new hardware approaches to enhance analytics speed and efficiency. Furthermore, processing units are now much faster than memory, so applications with large volumes of data are increasingly bottlenecked by memory accesses. This research, therefore, focuses on memory devices, in particular designing ``intelligent'' memory capable of computing results near the stored data, and proposes a solution by redesigning both hardware and software components of an analytics pipeline to work synergistically, addressing the data analytics performance issue from the ground up. This innovative approach has the potential to significantly improve the efficiency of data analytics. The project is a collaboration between one database and software researcher at the University of Wisconsin-Madison (UW) and two computer architecture and systems researchers at Cornell University and the University of Virginia (UVA). The project is organized into four thrusts. Thrust 1 aims to develop mechanisms for in-place data analytics query processing on the dynamic random access memory (DRAM) side and explore the synergies between intelligent DRAM and other processing units. Thrust 2 focuses on processing in memory (PIM) designs for static random-access memory (SRAM)-based caches, exploring associative processing (AP) and its applicability to data analytics workloads. Thrust 3 takes a holistic approach to accelerate analytics queries across both SRAM and DRAM-based PIM designs. It proposes a Domain-Specific Language (DSL)-based approach using an operational algebra, decomposing queries into a dataflow graph and optimizing their execution across different PIMs and the Central Processing Unit (CPU). Finally, Thrust 4 addresses the need for evaluation frameworks in the database-hardware co-design approach by developing a simulation infrastructure and benchmarks that can be used by the broader architecture and database research communities. Besides training students involved in this project across the hardware-software boundaries, the project will also support outreach efforts in entrepreneurship education at UW. Additionally, there are outreach plans to Native American high school students through an effort at Cornell, and at UVA, the project will contribute to ongoing efforts to build long-term collaborations with Historically Black Colleges and Universities (HBCUs) and Minority-Serving Institutions (MSIs) in the Virginia area. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.