FET: Small: CMOS+X: Integration of CMOS and voltage-controlled magnetic tunnel junctions for probabilistic computing

The fast growth of artificial intelligence applications currently outpaces the advances in their underlying semiconductor-based hardware. As a result, there is an urgent need for improved machine learning (ML) chips, which provide superior energy efficiency, reliability and security compared to existing solutions. At the same time, even with the best available computing hardware today, many important optimization problems cannot be solved using known algorithms in an efficient and scalable manner. Examples are the Boolean satisfiability, traveling salesman, and integer factorization problems, which have important applications ranging from microelectronic chip design to drug discovery, logistics, transportation, and cryptography. This project aims to develop application-specific integrated circuit (ASIC) prototypes that solve these problems using the physics of appropriately designed probabilistic circuits. These ASICs represent a physics-inspired and domain-specific computing architecture, where hardware and software are co-designed to solve a specific problem which cannot be efficiently solved – using finite time and energy resources – on any general-purpose classical computing chip. The project is expected to impact a wide range of artificial intelligence and optimization applications across various industries, while also providing new fundamental insights into the emerging class of probabilistic computing architectures. In addition to its research objectives, a key goal of this project is also workforce development for advanced semiconductor technologies. Research results will also be incorporated into new course materials being developed at Northwestern University. This project will develop integrated circuits where complementary metal-oxide silicon (CMOS) circuits are integrated with voltage-controlled magnetic memory devices, which will serve as ultrafast true random number generators. The chips are aimed for two application areas which will be investigated in this project: (A) Low-power machine learning processors based on probabilistic circuits: Convolutional neural networks require large numbers of transistors and high-power dissipation. The researchers will develop a stochastic computing implementation of neural networks integrated with magnetic memory devices, which simplifies the multiplication and addition operations, resulting in significant reduction of power consumption and chip area. (B) Combinatorial optimization processors based on probabilistic circuits: This project will also develop probabilistic optimization circuits where the optimization problem of interest is mapped onto an appropriately designed network of probabilistic bits on the ASIC. The performance and efficiency of the ASICs for both problems will be compared to existing general-purpose computing hardware. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.