SHF: Small: Redesigning the Memory System in the Era of Compute Express Link

Modern computing systems contain a variety of heterogeneous processing units, such as central processing units (CPUs), graphics processing units (GPUs), and specialized hardware accelerators. The performance of these units is often dictated by the memory system’s capacity and bandwidth. While Dual-Data Rate (DDR) has been the de facto memory interface for the last three decades, the technological landscape is changing to accommodate the increasing demands put on the memory system. After several years of competition among new interconnect technologies, Compute Express Link (CXL) is establishing itself as the winner, with widespread industry adoption. CXL is well-positioned to change the way high-performance computing systems are built and deployed, in part due to its versatility: the same interconnect technology can be used to connect processors with peripheral devices, specialized hardware accelerators, and memory expansion devices. The crucial observation driving the project’s intended research is that CXL-centric or CXL-augmented memory systems bear characteristics that cater well to the growing memory capacity and bandwidth demands of workloads prevalent in datacenter and high-performance computing environments, and therefore have transformational potential for computing systems with crucial commercial significance in modern digital economies. In addition to contributing new system designs that improve system performance and efficiency, the project’s activities will enrich educational activities, introducing the student body and future workforce to the emerging CXL technology. The project will investigate new memory system organizations enabled by CXL. The investigators will pursue opportunities in leveraging CXL’s (i) bandwidth superiority as a potential replacement for conventional DDR-attached memory in bandwidth-constrained systems; (ii) ability to enable disaggregated, selectively shareable memory across multiple hosts to develop new architectures that deliver superior performance via effective sharing of a common memory pool; and (iii) ability to multiplex memory and I/O traffic to improve the efficiency of bandwidth-intensive systems. Finally, the project will investigate new fault tolerance and data placement challenges that emerge in the presence of hybrid CXL-DDR memory systems, and develop new software and hardware techniques to address them. The project’s activities will produce methodologies to study such new memory systems, and evaluate novel CXL-enabled memory architectures that improve the performance, efficiency, and workload consolidation capability of commercially crucial systems used in datacenter and high-performance computing environments. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.