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Directorate for EngineeringNSF · NSFNSF

EAGER: Lock-in IR Thermography for Thermal Resistance Characterization of Interconnects in 3D Die Stacks

David G Cahill·University of Illinois at Urbana-Champaign, IL·2024–2026·ACTIVE
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INSTITUTION

University of Illinois at Urbana-Champaign, IL

PRINCIPAL INVESTIGATOR

David G Cahill

FUNDING

$300K

YEAR

2024

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Abstract

High performance microelectronic devices require stacking of individual silicon dies into complex three-dimensional assemblies to meet the needs of high rates of data transfer between logic and memory. Interfaces between dies, however, create thermal resistances that impede the transfer of up to 1 kilowatt of heat from the three-dimensional device into the adjacent heat exchanger. Limitations on device performance that are imposed by inadequate heat transfer are ubiquitous in the microelectronics industry. Thermal metrology tools that are applicable in an industrial setting will improve the ability of engineers to design thermal management solutions, monitor assembly processes, and analyze failure mechanisms. The objective of this project is to advance the science and engineering of thermal property measurement and develop a metrology tool that can meet the needs of industry. This work will also provide training for PhD students in the science and engineering of thermal management in the microelectronics industry. This project will develop lock-in infrared thermography for the measurement of thermal resistances in three-dimensional integrated circuits. Lock-in infrared thermography leverages recent advances in high performance infrared cameras and can effectively address the measurement challenges outlined above. A key aspect of the research is the development and validation of an analytical model for heat conduction in multilayer die stacks and the refinement of a measurement approach to rapidly acquire data and extract the thermal resistance of individual interconnect layers. The outcomes of the research will include improved metrology tools that will accelerate research and development in the packaging and thermal management of microelectronics. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Directorate for EngineeringEAGERTTP-Thermal Transport ProcessTHERMAL TRANSPORT PROCESSESthroughincludeneedsdimensionalprocesseslayerslimitationsleveragesassemblyimpedeworthyreflectsindustrialmeritcircuitscomplexrecentmanagementmicroelectronicsexchanger

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