SaTC: CORE: Medium: Verifiable Secure Hardware Design via Game-Theoretic and Cryptographic Primitives

System-on-Chips (SoCs) are essential components of critical digital systems across domains such as healthcare, autonomous vehicles, and national infrastructure. As SoCs grow in complexity, they increasingly become targets for sophisticated hardware attacks that threaten privacy, safety, and national security. The project's novelties lie in developing a proactive and intelligent framework for securing SoCs against power side-channel and fault injection attacks, that not only respond to known threats but also anticipate and mitigate potential risks before they can materialize. The project's broader significance and importance are in enabling early-stage, verifiable security integration into the chip design process-shifting the research from reactive defense to built-in assurance. The project also contributes to open-source tools, student training, and the cultivation of a workforce capable of designing secure hardware systems. This project uses reinforcement learning and game theory to model evolving attacker-defender strategies and to automatically explore the SoC design space for secure hardware design configurations. It integrates advanced cryptographic primitives to enable security validation without revealing sensitive design details. The defense framework in this project is integrated into the SoC design and synthesis toolchain, allowing designers to trade-off between security, performance, power, and cost from the outset. The research advances foundational methods for secure hardware and is expected to produce new tools and practices for designing secure and high-assurance SoCs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.