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Directorate for Computer and Information Science and EngineeringNSF · NSFNSF

SHF: CSR: Medium: Practical and Efficient Accelerators with High-Frequency Chiplets

Baris Taskin·University of California-Santa Cruz, CA·2025–2029·ACTIVE
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INSTITUTION

University of California-Santa Cruz, CA

PRINCIPAL INVESTIGATOR

Baris Taskin

FUNDING

$1.0M

YEAR

2025

MOONBASE SCORE

Still being scored

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Abstract

Modern computer chip design faces a critical bottleneck: creating high-performance hardware accelerators requires countless manual iterations and expert-years of development time. This project addresses a national priority by developing automated Artificial Intelligence (AI) systems that can design high-frequency chips with minimal human intervention. The research focuses on Zero Knowledge Proof (ZKP) accelerators, a cutting-edge cryptographic technology that allows users to prove possession of information without revealing it—enabling privacy-preserving verification. The project brings together three complementary areas of expertise: high-frequency chiplet design, AI-powered design automation, and cryptographic applications. We will deliver a unified chiplet-based design flow by (i) co-designing deeply pipelined ZKP accelerators, (ii) developing rotary-clock architectures for stable multi-GHz clock distribution across heterogeneous dies, and (iii) building an Intelligent Design Agentic Programming (IDAP) framework. IDAP will consist of a Large-Language-Model (LLM)-augmented Electronic Design Automation (EDA) framework that leverages formal constraints and solver-guided optimization to explore code transformations beyond today’s tools. AI agents will iteratively navigate design trade-offs, such as pipeline depth, with verification checks to prevent invalid configurations. Prototype ZKP accelerator chips will be fabricated and benchmarked to validate performance gains and robustness. This integrated approach will yield an open blueprint for high-frequency chiplet accelerator design applicable to a broad range of compute-intensive applications. The resulting infrastructure will be an open and accessible setup with broader impacts on semiconductor workforce training. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Directorate for Computer and Information Science and EngineeringSoftware & Hardware FoundationDES AUTO FOR MICRO & NANO SYSTMEDIUM PROJECTrequiresthroughintelligencehumanallowsverificationleveragesunifiedrotaryworthyreflectspoweredexpertmerityearsresultingintensivechipswithoutprove

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