SBIR Phase II: Advanced Metrology System for Surface and Bonding Quality Control in Semiconductor Manufacturing

The broader impact of this Small Business Innovation Research Phase II project is to investigate and validate new semiconductor measurement methods that are more robust and capable than existing standards. In the high-stakes field of semiconductor manufacturing, where errors of just a few atoms can lead to chip failure, the ability to produce advanced hardware is limited by the precision of the tools used to measure it. This project aims to develop metrology systems that can detect surface errors at the atomic scale, addressing a critical need for next-generation AI and memory chips. Currently, much of the sophisticated tool production for this industry occurs overseas; this project seeks to pivot that expertise back to the United States. By advancing domestic capabilities in high-precision toolmaking, this research strengthens national competitiveness, secures the domestic supply chain, and creates high-skilled manufacturing jobs prepared for the future. The primary technical challenge of this project is to scale a high-precision measurement concept (previously 15 mm in Phase I) to a 300 mm area without losing the ability to detect atomic-level surface errors. While interferometry has been the industry standard for decades, it is often too delicate for modern factory floors due to sensitivity to vibration and air turbulence. This project proposes replacing it with a new concept: the structured light autocollimator (SLA). The SLA is a novel approach that combines the angular precision of an autocollimator with the three-dimensional (3D) mapping capabilities of structured light. By measuring the slope of a surface rather than the phase of light, the system remains stable in dynamic environments. The scope of this Phase II project is to transition the SLA from a laboratory demo to an industrial tool prototype ready to test in a chip fabrication facility. Research will focus on two main goals: first, perfecting the mapping of 300 mm surfaces to meet the needs of modern chip production; and second, developing an infrared version of the system. Since silicon is transparent to infrared light, this new version will allow manufacturers to "see through" wafers to inspect the quality of 3D-stacked chips. The high precision of the SLA method will allow semiconductor engineers to visualize structural errors in 3D stacked chips with a level of detail not previously possible. This project will provide a new physical framework for high-resolution surface mapping, directly supporting the next generation of semiconductor manufacturing. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.