REU SITE: WAVE SURF: Workforce Advancement in Verification and Emulation of Semiconductor Chips -- Undergraduate Research Fellowships

Semiconductor chips power nearly every aspect of modern life, from smartphones and medical devices to national defense systems and critical infrastructure. As these chips grow more complex, verifying that they function correctly and securely has become one of the most costly and time-consuming stages of development. At the same time, the United States faces a critical shortage of engineers trained in chip verification, a gap that threatens both economic competitiveness and national security. This project establishes a Research Experiences for Undergraduates (REU) Site at Texas A&M University to train the next generation of verification engineers and semiconductor researchers. Each summer, ten undergraduate students will participate in a ten-week immersive research program focused on chip verification and the application of artificial intelligence (AI) to semiconductor design evaluation. The project specifically targets students from community colleges, regional universities, and institutions with limited research infrastructure, with emphasis on first-generation college students, veterans, and students with no prior research experience. Participants will receive layered mentorship from faculty, graduate students, and industry professionals, along with professional development training in scientific communication, ethics, and career readiness. Industry partners will contribute guest lectures, mentorship, and site visits, connecting students directly to career pathways in the semiconductor workforce. By combining cutting-edge research training with inclusive recruitment and sustained post-program engagement, this project addresses a pressing national workforce need while broadening participation in a strategically vital field. This project engages undergraduate researchers in four interconnected themes spanning hardware security, performance analysis, design automation, and functional verification. The first theme develops scalable security verification frameworks that adapt fuzzing, formal analysis, and symbolic execution to detect vulnerabilities in hardware designs described at the register-transfer level and prototyped on field-programmable gate arrays. The second theme applies machine learning (ML) to processor performance debugging, training models to automatically detect and localize performance anomalies using hardware counter data, estimate fine-grained performance breakdowns from limited counter sets, and accelerate design simulation through early-run inference. The third theme investigates the use of large language models to automate chip design tasks, including hardware description language code generation, physical synthesis using open-source tool flows, and timing optimization. The fourth theme targets ML-driven functional verification, developing techniques for automated testbench generation, structure-aware coverage acceleration, multimodal failure triage that combines text and waveform data, and closed-loop testbench correction guided by dynamic bug mutation analysis. Students will work with commercial electronic design automation tools and open-source processor platforms, producing weekly progress reports, final presentations, and potential conference submissions. The program integrates structured mentorship, professional skills training, and industry exposure through site visits and seminars with engineers from leading semiconductor companies. An external evaluator will conduct formative and summative assessments, and participants will be tracked for five years to measure long-term impact on graduate school enrollment, research productivity, and career outcomes. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.