POSE: Phase I: Toward a Comprehensive and Extensible Infrastructure for Machine Learning-Driven High-Level Synthesis Design, Evaluation, and Benchmarking

High-Level Synthesis (HLS) is a design methodology that allows developers to create hardware systems, such as accelerators for artificial intelligence and data processing, using common programming languages. HLS improves productivity and accessibility, but fragmented tools, inconsistent evaluation practices, and the absence of shared, reproducible datasets hinder progress in HLS research and education. This project addresses these challenges by creating an open-source ecosystem that unifies tools, workflows, and datasets for HLS-based hardware design. By lowering technical and expertise barriers, the project enables students, software developers, and early-career researchers to participate helping to increase access to hardware innovation. The ecosystem promotes open science, reproducibility, and fair comparisons across platforms, strengthening national research infrastructure in computing and semiconductor design. Integration into university courses, capstone projects, summer schools, and online training programs support workforce development in advanced computing fields that are critical to national competitiveness. Although High-Level Synthesis (HLS) is increasingly used for hardware design, research in this area remains difficult to reproduce and compare due to fragmented toolchains, incompatible benchmarks, and inconsistent evaluation metrics. In addition, challenges are further amplified for machine learning and large language model (LLM)-based approaches. This project addresses these gaps by expanding an existing open-source framework into a modular open-source ecosystem for reproducible benchmarking, systematic design space exploration, and data-driven HLS research using machine learning (ML) and LLMs. The ecosystem provides unified interfaces for coordinating multiple HLS toolchains, standardized quality-of-result metrics across different Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuit (ASIC) targets, and scalable pipelines that generate large, structured datasets from limited seed designs. The project also supports consistent evaluation of automated and LLM-generated designs and offers extensible application programming interfaces for integrating new tools, hardware backends, datasets, and learning models. This ecosystem establishes a rigorous and adaptable foundation for reproducible, ML-enhanced hardware design using HLS. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.