High-Mobility Germanium-on-AlAs Nanosheet FETs and CFET for Adaptive and Ultra-Low-Power Electronics

High-Mobility Germanium-on-AlAs Nanosheet FETs and CFET for Adaptive and Ultra-Low-Power Electronics The continued push toward faster, smaller, and more energy efficient electronics requires new materials and device designs that can operate reliably at extremely small dimensions. Germanium (Ge) is an attractive semiconductor for future technologies because it allows electrical signals to move more quickly and with less energy than in silicon, the long standing foundation of the chip industry. However, building complete electronic systems from Ge, especially those that combine both n type and p type transistors in a single vertical stack, remains challenging. This project explores a new approach for creating high performance, ultra low power electronic devices by integrating Ge nanosheet transistors on a carefully engineered aluminum arsenide (AlAs) platform. This combination offers a promising path toward compact, energy efficient circuits that could benefit applications such as edge computing, adaptive sensing, and sustainable microelectronics. The research will deepen scientific understanding of how Ge based devices behave at extremely small scales, how heat flows through these structures, and how they can be combined into complete circuits. The project will also provide hands on research opportunities for undergraduate and graduate students, expand educational modules in semiconductor device engineering, and engage pre college learners through outreach programs, efforts that support the development of a diverse and skilled workforce prepared to contribute to the nation’s semiconductor and quantum innovation ecosystem. This project investigates high-mobility Ge-on-AlAs nanosheet field effect transistors (NSFETs) and vertically stacked complementary FET (CFET) architectures aimed at sub nanometer technology nodes. The research advances a unified materials to devices to circuits framework that addresses key challenges in monolithic Ge integration, including lattice compatibility, electrostatic control, thermal behavior, and circuit level performance. State-of-the-art materials synthesis using an ultra high vacuum molecular beam epitaxy platform will be used to develop stacked Ge-on-AlAs nanosheet structures and prototype devices. The work focuses on realizing high performance n-type and p-type Ge nanosheet transistors that leverage Ge’s superior carrier mobilities and on integrating these devices into a CFET configuration capable of low voltage operation. Predictive modeling using Synopsys TCAD and Verilog-HDL, calibrated through in house device development, will evaluate device behavior, quantify electrostatic control at small dimensions, and project CFET performance under realistic operating conditions. A central objective is the monolithic integration of p-Ge and n-Ge nanosheet structures on a Ge/AlAs/GaAs substrate, incorporating high-κ dielectric gate stacks to enable scalable operation at 0.5 V with minimal power consumption. Thermal effects will be incorporated directly into the simulation framework to assess temperature dependent performance metrics for both NSFET and CFET structures. At the circuit level, the project will explore device-informed, energy efficient designs, including inverters, ring oscillators, and 6T SRAM cells, based on the proposed Ge on AlAs CFET architecture. The anticipated outcomes include improved understanding of electrostatic behavior in stacked Ge nanosheet devices, validated models for thermal transport in CFET structures, and circuit level demonstrations of energy efficient operation that can guide future semiconductor design strategies. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.