Adaptive Oxide Switching Devices for Scalable ESD Protection in AI Driven Microelectronics

Electrostatic-discharge (ESD) protection has become a critical challenge for integrated circuits (ICs) at sub‑nm technology nodes. Conventional ESD solutions rely on P–N‑junction‑based conduction—such as diode-triggered paths—that inherently introduce parasitic leakage and unreliable mis-triggering behavior during ESD events. As device dimensions continue to shrink, these junction‑based structures face fundamental limitations, including leakage‑induced false activation, escalating fabrication complexity, and rising manufacturing costs. Electrostatic‑discharge failure remains one of the leading causes of integrated‑circuit (IC) reliability issues, accounting for nearly 30% of all IC failures. Unlike transistor dimensions, ESD phenomena do not scale with technology nodes, and every functional microelectronic chip—spanning high‑performance computing, memory, RF, sensors, healthcare devices, automotive electronics, power systems, aerospace hardware, and near‑field communication applications—requires robust ESD protection. With the rapid rise of AI workloads, device design and integration are accelerating a shift away from traditional processor‑centric (i.e., von Neumann) architectures toward decentralized, high‑performance in‑memory computing, which is highly dependent on emerging device–materials co-design. ESD protection circuits are indispensable and ubiquitous across modern electronics. While front‑end‑of‑line (FEOL) innovations have enabled this transition, reliability challenges are increasingly concentrated in back‑end‑of‑line (BEOL) interconnects, where maintaining high‑speed data integrity requires ESD protection that is both low‑capacitance and highly scalable. A materials‑to‑device paradigm shift is urgently needed to enable the next generation of robust, scalable ESD protection for microelectronic modules. This proposal aims to establish a new class of dielectric‑based ESD protection devices by integrating materials innovation, device physics, compact modeling, and circuit‑level design. The envisioned oxide‑switching ESD elements will deliver low‑power operation, high spatial resolution, and reconfigurable functionality in a non‑transistor form factor—paving the way for adaptive, scalable ESD protection tailored for AI‑driven microelectronics. The proposed work aims to design and fabricate a novel oxide‑based, non‑P–N‑junction passive ESD device featuring low clamping voltage, low capacitance, low leakage, and high scalability. Such a device addresses the pressing need for ESD protection elements with intrinsic rectification, reduced power consumption, fast response, and simplified fabrication compatible with both advanced technology nodes and emerging packaging processes for AI‑driven microelectronics. To meet the increasing demands of AI workloads, ESD device stability will be characterized and optimized through interface engineering and studies of transient responses within microstructures, which are intrinsically linked to material properties such as bandgap, dielectric constant, and thermal conductivity. The key areas of focus in this proposed work include (1) band‑structure emulation and exploration of new physics in CMOS‑compatible oxide ESD devices; (2) characterization of ultra‑scalable metal‑insulator‑silicon (MIS) and metal‑insulator‑metal (MIM) ESD devices for optimal rectification ratios and performance; (3) investigation of normally‑off operation with thermal stability and optimal ESD protection performance; and (4) integration‑aware modeling and circuit‑level design with transient response analysis for failure analysis and prediction. The successful outcome of this proposal will enable the demonstration of three CMOS‑compatible terminal devices that surpass the current state‑of‑the‑art ESD protection devices. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.