EAGER: Preventing Cross-Tenant Leakage from Persistent FPGA Hardware Memory and Enhancing Sub-OS Attack Resilience in Multitenant FPGA Clouds

Cloud computing increasingly relies on specialized programmable chips called Field-Programmable Gate Arrays (FPGAs) to accelerate applications such as artificial intelligence, financial analytics, and video processing. To improve efficiency and reduce costs, major cloud providers allow multiple customers to share the same FPGA over time. This shared-use model, however, introduces important security challenges. When one customer's workload finishes, sensitive information, including encryption keys and Artificial Intelligence (AI) model parameters, can remain in the FPGA's memory and potentially be recovered by the next user. In addition, hardware diagnostic interfaces originally intended for testing and maintenance can be exploited to gain privileged control of the device while bypassing software security mechanisms. This project develops system-level defenses that protect customer data throughout the FPGA lifecycle, addressing security vulnerabilities identified in current commercial platforms and responsibly disclosed to industry. By enabling more secure sharing of FPGA resources, the project supports broader adoption of hardware acceleration in the cloud, helping reduce energy consumption and infrastructure costs while strengthening the security of computing systems that underpin artificial intelligence, financial services, and other critical sectors. This project is investigating system-level security mechanisms that address residual data exposure and attacks that operate below the operating system across all FPGA memory types. A central focus of the project is the development of SCRUM (Secure Cleanup of Residual User Memory), a kernel-level framework that transparently intercepts process termination and securely sanitizes system and on-chip memory before resources are reallocated to subsequent tenants. Complementary efforts evaluate Rust-based software and hardware description toolchains to improve the correctness, reliability, and auditability of memory erasure routines. To defend against attacks that exploit hardware diagnostic interfaces, the project develops a hardware monitoring agent that operates at the highest processor privilege level, detects unauthorized processor resets and anomalous memory access patterns, and initiates a structured recovery process that includes targeted memory sanitization and partial FPGA reconfiguration. The project validates these defenses on production-grade platforms from major hardware vendors and releases the resulting software as open source to benefit the cloud security research and practitioner communities. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.