Secure Packaged Microelectronic Components, Printed Circuit Boards, and Supporting Technologies

Information Requested: The U.S. Army Combat Capabilities Development Command Aviation and Missile Center (DEVCOM AvMC), Redstone Arsenal, AL is conducting market research to identify domestic products, suppliers, designers and manufacturers of advanced protection architectures, systems, components, and other technologies for packaged microelectronics intended for deployment into current and future military systems of interest to the Department of Defense (DoD). This RFI is seeking information from suitable vendors/vendor teams related to the following Technology Areas: 1. Board-level Security: Capabilities spanning microelectronic components and portable soft IP integrated with commercial-off-the-shelf (COTS) devices across modular open systems architectures (MOSA) form factor systems (e.g., 3U/6U OpenVPX/SOSA, 3U/6U SpaceVPX, VNX, and smaller). 2. Package Security: Specialized microelectronics packaging configurations or designs for multi-chip modules (MCMs) or systems-in-package (SIPs) which utilize COTS or bespoke security components that are intended to provide additional security to underlying components. 3. Enhanced Secure Boot: Portable soft IP that can be used in conjunction with COTS microelectronic components to provide additional security for enhanced secure boot applications. 4. Secure Components: Purpose-designed microelectronic components (chiplets, ASICs, etc.) that are intended to provide enhanced trust/security for co-packaged microelectronic components. 5. Multi-chip Packaging: Advanced microelectronics packaging techniques that inherently provide additional component security or could be easily adapted to provide additional microelectronic component security. 6. Emerging Technologies: Novel techniques, materials, and processes that are compatible with modern microelectronic manufacturing/packaging methods that can provide additional security to packaged microelectronic components. 7. Other: Technologies, methods, and processes not mentioned above that are compatible with modern microelectronics design, manufacturing, and packaging techniques and able to provide enhanced security to packaged microelectronic components. For additional details refer to the Attachment, R2.0_SS_RFI_SUBMISSION_v1.2.