SHF: Small: Testing and Design-for-Test Techniques for Monolithic 3D Integrated Circuits

Fabrication of high-performance integrated circuits is relying increasingly on three-dimensional (3D) integration based on through-silicon vias (TSVs). However, fabrication constraints restrict the integration density that can be achieved using this technology. A recent innovation called Monolithic 3D (M3D) integration has the potential to achieve higher device density and performance compared to 3D stacking based on TSVs. This project seeks to develop efficient ways to test M3D-based integrated circuits, by targeting testing and 'design-for-test' (DfT) methods. Advances in testing and DfT will enable high reliability and low defective-parts-per million, which will enhance the competitiveness of US semiconductor companies. Synergies between research on testing of M3D and on design tools and fabrication will foster a community of researchers and lead to further advances in M3D integration. High-school students from the North Carolina School of Science and Mathematics will be mentored though projects in this space. The outreach plan includes engagement with the Duke Technology Scholars Program, which targets women undergraduates early in their careers. The anticipated outcomes of this research are methodologies and tools to analyze, model, and screen manufacturing defects, as well as DfT solutions to enable testing, defect isolation, and yield enhancement. Research on testing and DfT for M3D is not only timely, but it is likely to find easy acceptance owing to zero legacy, and can therefore have a dramatic impact on research and industry practice. Specific research goals in this project include the following: (1) A built-in self-test (BIST) solution to detect and diagnose faults in inter-layer vias (ILVs) and the reuse of this BIST infrastructure for detecting faults in logic and memory tiers. (2) Design of BIST controllers for coordinating test application. (3) Test generation for delay faults introduced by device coupling in M3D, and defects in ILVs and the inter-layer dielectric. (4) Design of the power-distribution network to increase resilience to the problems of electromigration and stress migration. Close collaborations are underway with partners at leading companies and internationally renowned institutions in this field. Research findings will be integrated in VLSI design and testing courses at Duke and lecture materials will be made available to the broader community. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.