ASCENT: Large-Scale Electronic-Photonic Circuits with Heterogeneously Integrated Conductive Oxide for High-throughput and Energy-efficient Computing

Of all existing semiconductor platforms, silicon is undeniably the most critical one for heterogeneous integration between photonic and electronic integrated circuits that can revolutionize future semiconductor systems. The aim of this ASCENT project focuses on energy-efficient silicon photonic circuits with co-designed electronic application-specific integrated circuits by heterogeneously integrating high-mobility transparent conductive oxide through wafer- and panel-scale manufacturing. The approach is compatible with existing silicon photonics fabrication and will result in unprecedented improvement in energy efficiency and bandwidth density through innovative materials, device design, electronic-photonic optimization and packaging. This project also generates broad impacts on workforce development by providing unique opportunities for training and education of graduate and undergraduate students through the proposed foundry-university co-fabrication and unique co-integration approach. Students will benefit from collaboration with industry by participating in summer internships to receive hands-on experiences in circuit design, device fabrication, optoelectronic integration, and high-speed characterization. Leading-edge applications such as artificial intelligence (AI), 6G-and-beyond communications, quantum and neuromorphic computing have unmet requirements on energy efficiency and bandwidth density. This ASCENT project targets this challenge by an interdisciplinary team with complementary expertise in photonic devices, electronic circuits, and system-level integration. Specifically, the team will develop a wavelength division multiplexing photonic transceiver consisting of silicon microring modulator array and tunable optical filter array coupled with resonant nano-photodetectors, capable of achieving 10 terabits per second full-duplex bidirectional link with 100 femto-joule per bit system-level energy efficiency. The core photonic engine is driven by a metal-oxide-semiconductor capacitor structure with athermal titanium dioxide cladding, which will be packaged with sub-volt electronic driver circuits. Additionally, the project will address critical fabrication challenges through combining commercial silicon photonic foundries with university fabrication and packaging to prove the feasibility of commercialization. The team will also demonstrate critical steps for wafer- and panel-scale integration such as RF-sputtering, stepper lithography, and high-pitch-density packaging. The success of this project will elevate the performance of heterogeneously integrated semiconductor systems to meet the stringent requirement of future high-performance computing. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.