ACED Fab: Co-Design of Novel Electronic-Photonic Systems for Energy-Efficient Coherent Optical Interconnects

Dramatic improvements in datacenters and high-performance computing systems’ interconnect bandwidth-density and energy-efficiency are necessary to support advances in machine learning, artificial intelligence, sensor systems, and 5G/6G workloads. However, there are fundamental limitations to scaling data rates in conventional intensity-modulated direct detection (IMDD) optical links due to the extreme baud rates, i.e. changes in signals per second. Coherent optical interconnects offer a potential solution, as they modulate both the amplitude and phase of the optical carrier and utilize dual polarization (DP) operation to allow for a dramatic increase in bandwidth-density per wavelength. While coherent optical links are spectrally-efficient, key challenges include limited silicon photonic modulator bandwidth, high-power transceivers due to independent design of the photonic devices and front-end circuitry, sensitivity to photonic device fabrication variations, and high-power receiver-side optical carrier recovery that is commonly performed in a complex digital signal processor (DSP) block. This proposal addresses these important issues by co-designing high-bandwidth photonic devices and advanced-node CMOS front-ends that can adapt to variations in optical device performance and by utilizing a power-efficient receive-side carrier recovery scheme based on a dual-loop optical phased-locked loop (OPLL). The proposed technology will enable energy efficient coherent optical transceivers that will allow dramatic scaling in datacenter traffic capacity to support the unprecedented growth in networked devices driven by emerging applications such as connected automobiles, for example. This proposal’s research goal is to develop a coherent optical interconnect architecture with novel high-bandwidth quadrature modulators with thin-film LiNbO3 (TF-LN) Mach-Zehnder modulators (MZMs) and quadrature demodulators with graphene photodetectors. Co-design of energy-efficient CMOS transmitters with dynamic voltage frequency scaling (DVFS) with efficient switching regulators and energy-efficient CMOS receivers with DVFS, adaptive bandwidth front-ends, and auto-tuned quadrature demodulators will be fabricated to accomplish this goal. In addition, an optical phase-locked loop (OPLL) based carrier recovery scheme with wide-range electronic voltage-controlled oscillator (VCO) tuning will be developed. Applying the proposed technology will revolutionize the future of both datacenter and high-performance computing systems due to its ability to offer low-latency interconnects without error coding. This project will involve an interdisciplinary team of 2 Texas A&M University (TAMU) students and 3-4 National Chung Hsing University (NCHU) students. Two sets of prototypes will be implemented using two advanced CMOS processes, a silicon photonic process, and custom-fabricated thin-film TF-LN integrated circuits. Project outreach activities include exchange and visiting activities where TAMU and NCHU students work together face-to-face on-site during critical IC design phases and also participate in joint workshops, interactions with high school teachers via the Enrichment Experiences in Engineering (E3) program and introducing basic research concepts to PK-12 students through the Spark! Program. Project results will be broadly disseminated by inclusion in the syllabus and website of a new graduate course entitled "Coherent Optical Systems", the development of online modules for academia and industry, and through publication in national and international journals and conferences. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.