Collaborative Research: SaTC: CORE: Medium: Systematic Detection Of and Defenses Against Next-Generation Microarchitectural Attacks

It is difficult to compute on sensitive data without inadvertently leaking it to the wrong party. Making matters worse, processor design significantly exacerbates this problem. Specifically, processors are made up of performance optimizations (called microarchitecture). Research has shown how a savvy attacker can manipulate microarchitecture to leak sensitive data. This project’s novelties are to design methodologies and tools for analyzing microarchitecture through a security lens: capturing its potential to leak sensitive data and providing actionable feedback to hardware designers and software writers to help avoid sensitive data breaches at both hardware design time and software run time. The project’s broader impact and importance is to develop a means for building efficient, secure processors—i.e., those where performance and security are not mutually exclusive. The project is broken into two synergistic thrusts. Thrust 1, Analysis, develops techniques for understanding and succinctly characterizing the information leakage potential of microarchitectural components (at various stages in their development) when they are integrated into a larger design. Thrust 2, Hardening, develops techniques for using said characterizations (specifications), e.g., generated by thrust 1, to derive software mitigations. In both thrusts, a major goal is to develop techniques that can be automated. Correspondingly, by the end of the project, the goal is to develop and disseminate a complete end-to-end prototype framework that can be used alongside traditional hardware design flows to 1) enable security-efficiency co-design by hardware engineers and 2) protect programs when run on previously analyzed microarchitectures. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.